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电子工程专辑
3 年
如何用Python写Verilog?
事情是这样的,SoC工程师的一项典型工作就是集成。俗称连连看。 当然除了连连看还有一些集成级的代码需要设计,比如CRG,regfile,ahb/apb/local bus decoder,axi bus matrix/network等等。这些代码很多是有vendor提供工具生成,或者用脚本生成。集成工作我们前面介绍的 ...
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